american microsystems, inc. november 2000 this document contains information on a new product. specifications and information herein are subject to change without notice . 11.29.00 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1.0 features ? generates one bank of ten clock outputs (1y0 to 1y9) from one reference clock input (clk) ? designed to meet the pll component specifications as noted in the pc133 sdram registered dimm design specification ? external feedback input (fbin) to synchronize all clock outputs to the reference input ? operating frequency 25mhz to 140mhz ? tight tracking skew (spread-spectrum tolerant) ? on-chip 25 ? series damping resistors for driving point-to-point loads ? output enable (g) enables or disables low all clock outputs ? available with an auto power-down option that turns off the pll and forces all outputs low when the refer- ence clock stops ( fs612510-02 ) ? packaged in a 24-pin tssop figure 1: block diagram fs612510 1y0 1y1 1y2 1y3 1y4 1y5 1y6 1y7 1y8 pll fbin clk g fbout avdd 1y9 vdd gnd agnd 2.0 description the fs612510 is a low skew, low jitter cmos zero-delay phase-lock loop (pll) clock buffer ic designed for high- speed motherboard applications, such as those using 133mhz sdram. ten buffered clock outputs are derived from an onboard open-loop pll. the pll aligns the frequency and phase of all output clocks to the reference input clock clk, in- cluding an fbout clock that feeds back to fbin to close the loop. multiple power and ground supplies help reduce the effects of noise on device performance. all ten outputs 1y0 to 1y9 are enabled and disabled low by the active-high g signal. the pll can be bypassed for test purposes by pulling avdd to ground. figure 2: pin configuration 1 2 3 4 5 6 7 8 24 23 22 21 20 19 agnd vdd 1y0 avdd clk 9 10 11 12 gnd gnd 1y3 1y4 vdd g fbout 18 17 16 15 14 13 1y6 gnd 1y7 gnd 1y8 1y5 vdd fbin fs612510 1y1 1y2 vdd 1y9 table 1: function table input output pll avdd g clk 1y0-1y9 fbout hll l l hlh l h hh l l l zero-delay hhh h h lll l l llh l h lhl l l pll bypass lhh h h
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 2 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic table 2: pin descriptions key: ai = analog input; ao = analog output; di = digital input; di u = input with internal pull-up; di d = input with internal pull-down; dio = digital input/output; di-3 = three-level digital input, do = digital output; p = power/ground; # = active low pin pin type name description 3 do 1y0 clock output 4 do 1y1 clock output 5 do 1y2 clock output 8 do 1y3 clock output 9 do 1y4 clock output 15 do 1y5 clock output 16 do 1y6 clock output 17 do 1y7 clock output 20 do 1y8 clock output 21 do 1y9 clock output enabled by g 23 p avdd power supply / test mode enable. this pin provides the power supply to the internal pll. when the pin is pulled low, the pll is bypassed and the output clocks directly follow the input clock 1 p agnd pll supply ground 24 di clk reference clock input ( note: -02 version has a pull-down on this pin ) 13 di fbin feedback clock input; must be connected to fbout to complete the loop 12 do fbout feedback output clock 11 di g output enable stops all clocks (1y0 ? 1y9) in a low state when this pin is low 6, 7, 18, 19 p gnd ground for all clock outputs 2, 10, 14, 22 p vdd power supply for all clock outputs
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 3 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 3.0 device operation the fs612510 is a zero-delay buffer intended for use on buffered pc133 sdram dimms. the fs612510 precisely aligns the frequency and phase of the output clocks to the input clk by use of an on-chip phase-lock loop (pll). the pll generates up to 10 low- skew, low-jitter copies of the clk, with the outputs ad- justed for 50% duty cycle. the fbout clock must be hardwired to the fbin pin to complete the loop. the pll actively adjusts the output clocks so that there is no phase error between the refer- ence clock (clk) and the feedback clock (fbin). since the device uses a pll to lock the output clocks to the input clock, there is a power-up stabilization time that is required for the pll to achieve phase lock. note that all inputs and outputs use lvcmos signal lev- els. 3.1 pll bypass when the avdd pin is pulled low, the reference clock signal bypasses the pll and is muxed directly through to the outputs. the pll is powered down, and device acts a fanout buffer. note that if avdd is re-established, the pll requires a power-up and stabilization time to lock to the input clock. 3.2 output enable/disable all ten outputs are enabled or disabled as a group by the g enable signal. a logic-high on g input enables all the clock outputs to swing in phase with the reference clock. a logic-low on g forces all of the clock outputs to a logic-low state. the function table table 1 shows the effect of the g en- able signal on the clock outputs. 3.3 power-down the fs612510-02 version provides an auto power-down feature that shuts off the pll, drives all outputs low, and places the device into a low current state if the reference clock stops. the power-down circuit is level sensitive, and detects either a dc high or low on the clk input. 4.0 tracking skew pll-based buffer ics may be required to follow a spread- spectrum modulated reference clock for frequencies greater than 66mhz. spread spectrum modulation limits peak emi emissions by intentionally introducing jitter onto a clock signal, effectively spreading the peak energy over a range of frequencies. a downstream pll, contained in a clock buffer ic such as this one, must carefully track the modulated input ref- erence clock. a measure of how closely the downstream pll follows the modulated clock is called the tracking skew. to ensure a tight tracking skew, the loop band- width of a downstream pll is increased and the loop phase angle is reduced over that of typical pll-based clock generators. the type of modulation profile used impacts tracking skew. the maximum frequency change occurs at the profile limits where the modulation changes the slew rate polarity. to track the sudden reversal in clock frequency, the downstream pll must have a large loop bandwidth. the ability of the downstream pll to catch up to the modulating clock is determined by the loop transfer func- tion phase angle. the spread-spectrum reference clock should be either a triangle-wave or a non-linear (lexmark) modulation pro- file, with a modulation frequency of 50khz or less.
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 4 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 5.0 electrical specifications table 3: absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. exposure to maximum rati ng conditions for extended conditions may affect device performance, functionality, and reliability. parameter symbol min. max. units supply voltage, dc, clock buffers (v ss = ground) av dd v ss - 0.5 7 v supply voltage, dc, core v dd v ss - 0.5 7 v input voltage, dc v i v ss - 0.5 v dd +0.5 v output voltage, dc v o v ss - 0.5 v dd +0.5 v input clamp current, dc (v i < 0 or v i > v dd )i ik -50 50 ma output clamp current, dc (v i < 0 or v i > v dd )i ok -50 50 ma storage temperature range (non-condensing) t s -65 150 c ambient temperature range, under bias t a -55 125 c junction temperature t j 125 c lead temperature (soldering, 10s) 260 c static discharge voltage protection (mil-std 883e, method 3015.7) 2 kv caution: electrostatic sensitive device permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. table 4: operating conditions parameter symbol conditions/description min. typ. max. units supply voltage, core and outputs v dd 3.3v 10% 3.0 3.3 3.6 v ambient operating temperature range t a 070c output load capacitance c l 15 pf input frequency f clk clk 50 140 mhz input duty cycle clk 40 60 % input rise/fall time clk 3 ns
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 5 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic table 5: dc electrical specifications unless otherwise stated, all power supplies = 3.3v%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal charac- terization data and are not currently production tested to any specific limits. min and max characterization data are 3 from typical. negative currents indicate current flows out of the device. parameter symbol conditions/description min. typ. max. units overall supply current, dynamic f clk = 133.33mhz; v dd = 3.3v 135 ma supply current, static i ddl outputs low; v dd = 3.3v 3 ma output enable input (g) high-level input voltage v ih 2.0 v dd +0.3 v low-level input voltage v il v ss -0.3 0.8 v input leakage current i i -5 5 a clock inputs (clk, fbin) high-level input voltage v ih 2.0 v dd +0.3 v low-level input voltage v il v ss -0.3 0.8 v -01 version -5 5 input leakage current i i -02 version has a pull-down on clk 28 a input loading capacitance * c l(in) as seen by an external clock driver 4 pf clock outputs (1y0:9, fbout) v dd = 2.9v, v o = 2.0v -18 -12 high-level output source current i oh v dd = 3.7v, v o = 2.0v -35 -12 ma v dd = 2.9v, v o = 0.8v 12 16 low-level output sink current i ol v dd = 3.7v, v o = 0.8v 12 17 ma output impedance z o 33 ? tristate output current i oz -10 10 a short circuit source current * i osh v o = 0v; shorted for 30s, max. -60 ma short circuit sink current * i osl v o = 3.3v; shorted for 30s, max. 90 ma table 6: clock output drive (1y0:4, 2y0:3, fbout) voltage low drive current (ma) high drive current (ma) 0.1 v -47 -59 2 2 0.2 v -45 -58 4 4 0.4 v -43 -56 8 9 0.6 v -40 -55 12 13 0.8 v -38 -52 16 17 1.0 v -35 -50 20 21 1.2 v -32 -47 24 25 1.4 v -29 -45 27 29 1.6 v -26 -41 31 33 1.8 v -22 -38 34 36 2.0 v -18 -35 38 40 2.2 v -15 -31 41 43 2.4 v -10 -28 43 46 2.6 v -6 -24 45 49 2.8 v -2 -20 48 51 3.0 v 0 -15 49 53 3.3 v -9 56 3.6 v -2 59 -60 -45 -30 -15 0 15 30 45 60 00.511.522.533.5 output voltage (v) output current (ma) 30? 50? 90?
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 6 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic table 7: ac timing specifications unless otherwise stated, all power supplies = 3.3v, no load on any output, and ambient temperature t a = 25c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 from typical. parameter symbol conditions/description min. typ. max. units overall skew, output to output * t sk(o) measured on the rising edge at 1.65v; c l = 15pf 150 ps skew, tracking * measured using a ?0.5% 31.5khz spread spectrum reference clock at 133.33mhz 150 ps static phase error * from rising edge on clk to rising edge on fbin -120 ps clock stabilization time * time required for the pll to achieve phase lock 3 ms loop bandwidth * for calculation of tracking skew 1.2 mhz phase angle * for calculation of tracking skew -0.031 clock outputs (1y0:9, fbout) duty cycle * d t ratio of high pulse width to one clock period, measured at 1.65v 45 55 % jitter, cycle-cycle * t j(cc) adjacent cycles at 1.65v -75 +75 ps jitter, period (peak-peak) * t j( ? p) from rising edge to next rising edge at 1.65v rise time * t r v o = 0.4v to 2.0v; c l = 15pf 1.2 ns fall time * t f v o = 2.0v to 0.4v; c l = 15pf 1.4 ns enable delay * t dlh via g 1 10 ns disable delay * t dhl via g 1 10 ns figure 3: clock skew measurement clock skew (t sk(o) ) any output any output 50% v dd 50% v dd figure 4: phase error measurement phase error clk fbin 50% v dd 50% v dd figure 5: timing measurement points 0.4v 2.4v 3.3v d t t f t r 50% v dd figure 6: output enable measurement t dlz v ol v oh v ss v dd 10% 90% t dhz 50% 50% 50% 50% t dzl t dhz output enable output
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 7 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 6.0 package information table 8: 24-pin tssop package dimensions dimensions inches millimeters min. max. min. max. a - 0.047 - 1.20 a 1 0.002 0.006 0.05 0.15 a 2 0.0315 0.0413 0.80 1.05 b 0.0075 0.0118 0.19 0.30 c 0.0035 0.0079 0.09 0.20 d 0.303 0.311 7.70 7.90 e 1 0.169 0.177 4.30 4.50 e 0.252 6.40 bsc e 0.0256 0.65 bsc l 0.0177 0.0295 0.45 0.75 s 0.0079 - 0.20 - 1 0 8 0 8 2 12 ref 12 ref 3 12 ref 12 ref american microsystems, inc. be d a 1 seating plane base plane a 2 a c l 1 3 2 s e e 1 1 24 table 9: 24-pin tssop package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air ja air flow = 0 m/s 84 c/w lead inductance, self l 11 longest lead 1.7 nh l 12 longest lead to any 1 st adjacent lead 0.6 lead inductance, mutual l 13 longest lead to any 2 nd adjacent lead 0.24 nh lead capacitance, bulk c 11 longest lead to v ss 0.3 pf c 12 longest lead to any 1 st adjacent lead 0.1 lead capacitance, mutual c 13 longest lead to any 2 nd adjacent lead 0.007 pf
american microsystems, inc. november 2000 iso9001 iso9001 iso9001 iso9001 qs9000 qs9000 qs9000 qs9000 8 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 FS612510-01/-02 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 1:10 zero-delay clock buffer ic 7.0 ordering information table 10: device ordering codes device number ordering code package type operating temperature range shipping configuration FS612510-01 12055-102 24-pin tssop (thin shrink small outline package) 0 c to 70 c (commercial) tape and reel fs612510-02 12055-103 24-pin tssop (thin shrink small outline package) 0 c to 70 c (commercial) tape and reel copyright ? 2000 american microsystems, inc. devices sold by ami are covered by the warranty and patent indemnification provisions appearing in its terms of sale only. ami makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the fr eedom of the described devices from patent infringement. ami makes no warranty of merchantability or fitness for any purposes. ami re - serves the right to discontinue production and change specifications and prices at any time and without notice. ami?s products are intended for use in commercial applications. applications requiring extended temperature range, unusual environmental require- ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom- mended without additional processing by ami for such applications. american microsystems, inc., 2300 buckskin rd., pocatello, id 83201, (208) 233-4690, fax (208) 234-6796, www address: http://www.amis.com e-mail: tgp@amis.com
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